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W147 Datasheet

  • W147

  • Frequency Generator for Integrated Core Logic

  • 12頁(yè)

  • CYPRESS

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PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?Low jitter and tightly controlled clock skew
鈥?Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
鈥?Three copies of CPU clock at 66/100 MHz
鈥?Nine copies of 100-MHz SDRAM clocks
鈥?Eight copies of PCI clock
鈥?Two copies of synchronous APIC clock
鈥?Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
鈥?Two copies of 66-MHz fixed clock
鈥?One copy of 14.31818-MHz reference clock
鈥?Power-down control
鈥?I
2
C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................鹵0.5 ns
Table 1. Pin Selectable Functions
SEL1
0
0
1
1
SEL0
0
1
0
1
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
VDDQ3
Pin Configuration
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWRDWN#
SCLK
SDATA
SEL1
X1
X2
XTAL
OSC
PLL REF FREQ
REF/APICDIV
VDDQ2
SDATA
SCLK
I
2
C
Logic
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
CPU2_ITP
APIC0:1
VDDQ3
W147G
2
SEL0:1
PLL 1
2
3V66_0:1
PCI0_ICH
7
PCI1:7
DCLK
PWRDWN#
8
SDRAM0:7
PLL2
VDDQ3
USB
DOT
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
October 13, 1999, rev. **

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