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W137 Datasheet

  • W137

  • Bx Notebook System Frequency Synthesizer

  • 10頁

  • CYPRESS

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W137
Bx Notebook System Frequency Synthesizer
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum Technology
鈥?Two copies of CPU output
鈥?Six copies of PCI output (Synchronous w/CPU output)
鈥?One 48-MHz output for USB support
鈥?One selectable 24-/48-MHz output
鈥?Two Buffered copies of 14.318-MHz input reference
signal
鈥?Supports 100-MHz or 66-MHz CPU operation
鈥?Power management control input pins
鈥?Available in 28-pin SSOP (209 mils)
鈥?SS function can be disabled
鈥?See W40S11-02 for 2 SDRAM DIMM support
PCI_F, PCI1:5 Output to Output Skew:........................ 500 ps
PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps
CPU to PCI Output Skew: ............... 1.5鈥?.0 ns (CPU Leads)
Output Duty Cycle: .................................................... 45/55%
PCI_F, PCI Edge Rate: .............................................. >1 V/ns
CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#,
PWR_DWN# all have a 250-k鈩?pull-up resistor.
Table 1. Pin Selectable Frequency
SEL100/66#
0/1
0
1
OE
0
1
1
CPU
HI-Z
66.6 MHz
100 MHz
PCI
HI-Z
33.3
33.3
Spread%
Don鈥檛 Care
See
Table 2
See
Table 2
Key Specifications
Supply Voltages: ....................................... V
DDQ3
= 3.3V鹵5%
V
DDQ2
= 2.5V鹵5%
CPU0:1 Output to Output Skew: ................................ 175 ps
CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps
Table 2. Spread Spectrum Feature
SPREAD#
0
1
Spread Profile
鈥?.5% (down spread)
0% (spread disabled)
Block Diagram
X1
X2
CPU_STOP#
Pin Configuration
2
REF0:1
XTAL
OSC
STOP
Clock
Logic
4
CPU0:3
2
SPREAD#
SEL0
SEL1
SEL133/100#
梅2
CPUdiv2_0:1
PLL 1
梅2/梅1.5
STOP
Clock
Logic
4
3V66_0:3
GND
X1
X2
PCI_F
PCI1
PCI2
GND
VDDQ3
PCI3
PCI4
PCI5
VDDQ3
48MHz
24/48MHz/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDQ3
REF0/SEL48#
REF1/SPREAD#
VDDQ2
CPU0
CPU1
GND
GND
PCI_STOP#
VDDQ3
CPU_STOP#
PWR_DWN#
SEL100/66#
GND
1
PCI_F
STOP
Clock
Logic
7
PCI1:7
PWRDWN#
PCI_STOP#
梅2
Power
Down
Logic
3
梅2
IOAPIC0:2
Three-state
Logic
PLL2
1
48MHz
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
October 12, 1999, rev. **

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