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W127 Datasheet

  • W127

  • Clocks and Buffers

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  • ETC

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PRELIMINARY
W127/W127-A
Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?I
2
C interface
鈥?Four copies of CPU Output
鈥?Six copies of PCI Output
鈥?Two copies of AGP Output
鈥?One copy of 48-MHz USB Output
鈥?One copy of 24-MHz SIO Output
鈥?Twelve copies of SDRAM Output
鈥?One buffered copy of 14.318-MHz reference input
鈥?Mode input pin selects optional power management in-
put control pins (reconfigures pins 29, 30, 31, and 32)
鈥?Smooth frequency transition upon frequency
reselection
鈥?Available in 48-pin SSOP (300 mils)
鈥?Standard W127 device supports up to 112-MHz opera-
tions. High-performance option W127-A supports up to
124-MHz.
CPU Cycle to Cycle Jitter: ...........................................250 ps
CPU to AGP Skew: .................................................0鹵500 ps
AGP to PCI Skew: .................................. 1.5 ns (AGP Leads)
CPU Output Edge Rate: ............................................ >1 V/ns
SDRAM Output Edge Rate:.................................... >1.5 V/ns
Note:
All skews are optimized @V
DDQ2
= V
DDQ3
= 3.3V鹵5%.
Skews are not guaranteed for V
DDQ2
= 2.5V.
Table 1. Pin Selectable Frequency
[1]
Input Address
FS2
0
0
0
0
1
1
1
1
Supply Voltages: .......... V
DDQ3
= 3.3V, V
DDQ2
= 3.3V or 2.5V
.
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU
(MHz)
68.5
112
95.25
100
83.3
75.0
124
66.6
AGP
(MHz)
68.5
74.6
63.5
66.6
55.53
75
82.6
66.6
PCI
(MHz)
34.25
37.3
31.75
33.3
27.77
37.5
41.3
33.3
Key Specifications
Block Diagram
SDATA
SCLOCK
Serial Port
Device
Control
PLL Ref
Freq
X1
X2
XTAL OSC
I/O
PLL1
(CPU_STOP#)
梅1
梅1.5
CPU
STOP
SDRAM
STOP
VDDQ3
REF/SD_SEL
VDDQ2
CPU0:3
4
VDDQ3
SDRAM0:11
12
Pin Configuration
[2]
VDDQ3
VDDQ3
REF/SD_SEL*
GND
X1
X2
VDDQ3
PCI_F/FS2*
PCI0
GND
PCI1
PCI2
PCI3
PCI4
GND
GND
AGP_F/MODE*
AGP0
VDDQ3
SDRAM11
SDRAM10
VDDQ3
SDATA
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48MHz/FS1*
24MHz/FS0*
GND
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4(AGP_STOP#)*
SDRAM5(PWR_DWN#)*
SDRAM6(CPU_STOP#)*
SDRAM7(PCI_STOP#)*
GND
SDRAM8
SDRAM9
SCLOCK
W127/W127-A
AGP_F/MODE
梅2
(AGP_STOP#)
PCI
STOP
(PCI_STOP#)
(PWR_DWN#)
Power Down
Control
梅1
PLL2
梅2
I/O
I/O
AGP
STOP
I/O
AGP0
PCI_F/FS2
I/O
/
PCI0:4
5
VDDQ3
48MHZ/FS1
24MHZ/FS0
Notes:
1. Configuration 鈥?10鈥?is supported by W127-A only (see shaded row of
Table 1).
2. Signal names with 鈥?鈥?denote pins have internal 250K pull-up resistor, though not relied upon for pulling to V
DDQ3
. Signal names with parenthesis denote function
is selectable by MODE pin strapping.
Cypress Semiconductor Corporation
Document #: 38-07225 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002

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  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
    Cypress

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