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12-Bit, 21-MSPS, Analog-to-Digital
Converter
Low Power: 70 mW Minimum
Power-Down Mode: 4 mW
Low Input-Referred Noise: 75-dB
SNR Typical at 0-dB Gain
Novel Optical-Black (OB) Calibration
Low-Aperture Delay
Single 3-V Supply Operation
DNL: <鹵0.5 LSB and
INL: <鹵1.5 LSB Typical at 0-dB Gain
Programmable-Gain Range: 0 dB to 36 dB,
Gain Resolution of 0.05 dB/Step
48-Pin TQFP Package
PIN ASSIGNMENTS
PACKAGE
(TOP VIEW)
SCLK
SDIN
SLOAD
SCKP
STBY
RESET
48 47 46 45 44 43 42 41 40 39 38 37
OE
AVSS
AVDD
REFM
REFP
ISET
APPLICATIONS
Digital Still Camera
Digital Video Camera
D0/SDO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
DACO2
AVSS
DACO1
AVDD
TP2
PIN
DIN
TP1
CLREF
AVDD
AVSS
VSS
DESCRIPTION
The VSP1221 is a highly-integrated mixed-signal IC
used for signal conditioning and analog-to-digital
conversion at the output of a CCD array. The IC has
a correlated double sampler (CDS) and an analog
programmable-gain amplifier (PGA) stage followed by
an analog-to-digital converter (ADC) and a digital
PGA stage. The CDS is used to sample the CCD
signal and is followed by the analog PGA stage. The
ADC is a12-bit, 21-MSPS pipelined ADC. The digital
PGA provides further amplification.
Additionally, there is an offset calibration loop for
optical-black correction. The optical-black reference
level is user-programmable. The chip also has two
8-bit digital-to-analog converters (DAC) for external
analog settings.
The chip has a serial port for configuring internal
control registers.
The VSP1221 is available in a 48-pin TQFP package
and operates from a single 3-V power supply.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DIVDD
DIVSS
DVSS
ADCCLK
DVDD
CFG1
BLKG
CLPOB
SHP
SHD
CLPDM
CFG2
Copyright 漏 2001鈥?004, Texas Instruments Incorporated