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VSC834UB Datasheet

  • VSC834UB

  • Interface IC

  • 16頁(yè)

  • ETC

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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC834
Features
鈥?17 Input by 17 Output Crosspoint Switch
鈥?2.5Gb/s NRZ Data Bandwidth
鈥?42 Gb/s Aggregate Bandwidth
鈥?TTL Compatible
碌
P Interface
鈥?Differential PECL Data Inputs
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
鈥?On-Chip 50
鈩?/div>
Input Terminations
鈥?50
鈩?/div>
Source Terminated PECL Output Drivers
鈥?Single 3.3V Supply
鈥?9W Maximum Power Dissipation
鈥?High Performance 256-Pin BGA Package
General Description
The VSC834 is a monolithic 17x17 asynchronous crosspoint switch designed to carry broadband data
streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor inter-
face that allows random access programming of each output port. A high degree of signal integrity is main-
tained through the chip through fully differential signal paths.
The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 17:1
multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be pro-
grammed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The
signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input.
Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An inter-
rupt pin is provided to signal LOA, after which an external controller can query the chip to determine the chan-
nel(s) on which the fault occurred.
Each output driver is a fully differential switched current driver with on-die back-terminations for maxi-
mum signal integrity. Data inputs are terminated on die through 50
鈩?/div>
resistors connected to V
TERM
.
The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with
a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and
programming. Program buffering is provided to allow multiple program assignments to be queued and issued
simultaneously via a single configure command.
VSC834 Block Diagram
A0
Y0
A16
Control Logic
碌P
Interface
Y16
G52247-0, Rev 4.3
06/01/01
漏
VITESSE
SEMICONDUCTOR CORPORATION
鈥?741 Calle Plano 鈥?Camarillo, CA 93012
Tel: (800) VITESSE 鈥?FAX: (805) 987-5896 鈥?Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1

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    Logic IC
    ETC

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