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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7123 -
Extended Temperature Range
Features
鈥?802.3z Gigabit Ethernet Compliant 1.25 Gb/s
Transceiver
鈥?ANSI X3T11 Fibre Channel Compliant
1.0625 Gb/s Transceiver
鈥?0.98 Gb/s to 1.36 Gb/s Full-Duplex Operation
鈥?10-Bit TTL Interface for Transmit and
Receive Data
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
鈥?Operating Temperature Down to -40
o
鈥?RX Cable Equalization
鈥?Analog/Digital Signal Detection
鈥?JTAG Access Port for Testability
鈥?64-Pin, 10 mm TQFP Package
鈥?Single +3.3V Supply, 650mW Typical
General Description
The VSC7123 Extended Temperature Range (ETR) is a full-speed Fibre Channel and Gigabit Ethernet
Transceiver with industry-standard pinouts, which operates down to
鈭?/div>
40
o
. The VSC7123 ETR accepts 10-bit
8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL dif-
ferential outputs at a baud rate which is 10 times the REFCLK frequency. Serial data input on the RX PECL dif-
ferential inputs is resampled by the Clock Recovery Unit (CRU) and deserialized onto the 10-bit receive data
bus synchronously to complementary divide-by-twenty clocks. The VSC7123 ETR receiver detects 鈥淐omma鈥?/div>
characters for frame alignment. An analog/digital signal detection circuit indicates that a valid signal is present
on the RX input. A cable equalizer compensates for InterSymbol Interference (ISI) in order to increase maxi-
mum cable distances.
VSC7123 ETR Block Diagram
10
R(0:9)
QD
Serial to
Q Parallel D
梅10
QD
2:1
RX+
RX-
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
Clock
Recovery
梅20
Comma
Detect
Signal
Detect
Parallel
to Serial
DQ
DQ
TX+
TX-
REFCLK
x10 Clock
Multiply
NOT SHOWN: JTAG Boundary Scan
G52312-0, Rev 2.2
04/05/01
漏
VITESSE
SEMICONDUCTOR CORPORATION
鈥?741 Calle Plano 鈥?Camarillo, CA 93012
Tel: (800) VITESSE 鈥?FAX: (805) 987-5896 鈥?Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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