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V

E

Y

C IT

LO

TM

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7123

Features

鈥?802.3z Gigabit Ethernet-Compliant

1.25 Gb/s Transceiver

鈥?ANSI X3T11 Fibre Channel-Compliant

1.0625 Gb/s Transceiver

鈥?0.98 to 1.36 Gb/s Full-Duplex Operation

鈥?10-Bit TTL Interface for Transmit and

Receive Data

10-Bit Transceiver for Fibre

Channel and Gigabit Ethernet

鈥?Automatic Lock-to-Reference

鈥?RX Cable Equalization

鈥?Analog/Digital Signal Detection

鈥?JTAG Access Port for Testability

鈥?Single +3.3V Supply, 650mW Typical

鈥?Packages: 64-Pin 10mm and 14mm PQFP and

10mm TQFP

General Description

The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard

pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK

and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK

frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit

(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty

clocks. The VSC7123 receiver detects 鈥淐omma鈥?characters for frame alignment. An analog/digital signal

detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for

InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher

performance, lower cost replacement for the VSC7125 and VSC7135.

VSC7123 Block Diagram

10

R(0:9)

QD

Serial to

Q Parallel D

梅10

QD

2:1

RX+

RX-

RCLK

RCLKN

COMDET

ENCDET

EWRAP

SIGDET

T(0:9)

10

Clock

Recovery

梅20

Comma

Detect

Signal

Detect

Parallel

to Serial

DQ

DQ

TX+

TX-

REFCLK

x10 Clock

Multiply

NOT SHOWN: JTAG Boundary Scan

G52212-0, Rev 4.3

03/25//01

漏

VITESSE

SEMICONDUCTOR CORPORATION

鈥?741 Calle Plano 鈥?Camarillo, CA 93012

Tel: (800) VITESSE 鈥?FAX: (805) 987-5896 鈥?Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 1

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