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VS1003 Datasheet

  • VS1003

  • MP3 / WMA AUDIO CODEC

  • 57頁

  • ETC

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VS1003 PRELIMINARY
VS1003
VS1003 - MP3/WMA AUDIO CODEC
Features
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Decodes MPEG 1 & 2 audio layer III (CBR
+VBR +ABR); WMA 4.0/4.1/7/8/9 all pro-
鏗乴es (5-384kbps); WAV (PCM + IMA AD-
PCM);
General MIDI / SP-MIDI 鏗乴es
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Encodes IMA ADPCM from microphone
or line input
鈥?/div>
Streaming support for MP3 and WAV
鈥?/div>
Bass and treble controls
鈥?/div>
Operates with a single clock 12..13 MHz.
鈥?/div>
Internal PLL clock multiplier
鈥?/div>
Low-power operation
鈥?/div>
High-quality on-chip stereo DAC with no
phase error between channels
鈥?/div>
Stereo earphone driver capable of driving a
30鈩?load
鈥?/div>
Separate operating voltages for analog, dig-
ital and I/O
鈥?/div>
5.5 KiB On-chip RAM for user code / data
鈥?/div>
Serial control and data interfaces
鈥?/div>
Can be used as a slave co-processor
鈥?/div>
SPI 鏗俛sh boot for special applications
鈥?/div>
UART for debugging purposes
鈥?/div>
New functions may be added with software
and 4 GPIO pins
Description
VS1003 is a single-chip MP3/WMA/MIDI audio
decoder and ADPCM encoder. It contains a high-
performance, proprietary low-power DSP proces-
sor core VS DSP
4
, working data memory, 5 KiB
instruction RAM and 0.5 KiB data RAM for user
applications, serial control and input data inter-
faces, 4 general purpose I/O pins, an UART, as
well as a high-quality variable-sample-rate mono
ADC and stereo DAC, followed by an earphone
ampli鏗乪r and a ground buffer.
VS1003 receives its input bitstream through a se-
rial input bus, which it listens to as a system slave.
The input stream is decoded and passed through a
digital volume control to an 18-bit oversampling,
multi-bit, sigma-delta DAC. The decoding is con-
trolled via a serial control bus. In addition to the
basic decoding, it is possible to add application
speci鏗乧 features, like DSP effects, to the user RAM
memory.
mic
audio
line
audio
GPIO
VS1003
MIC AMP
4
GPIO
MUX
Mono
ADC
Stereo
DAC
Stereo Ear鈭?/div>
phone Driver
audio
L
R
output
X ROM
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Control
Interface
X RAM
VSDSP
4
Y ROM
RX
TX
UART
Y RAM
Clock
multiplier
Instruction
RAM
Instruction
ROM
Version 0.92, 2005-06-07
1

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