MC10E111, MC100E111
5V ECL 1:9 Differential
Clock Driver
The MC10E/100E111 is a low skew 1-to-9 differential driver,
designed with clock distribution in mind. It accepts one signal input,
which can be either differential or else single-ended if the V
BB
output
is used. The signal is fanned out to 9 identical differential outputs. An
enable input is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q outputs HIGH.
The device is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within-device, and empirical modeling is used to
determine process control limits that ensure consistent t
pd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50
鈩?
even if
only one side is being used. In most applications, all nine differential
pairs will be used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at least the output
pairs on the same package side (i.e. sharing the same V
CCO
) as the
pair(s) being used on that side, in order to maintain minimum skew.
Failure to do this will result in small degradations of propagation delay
(on the order of 10鈥?0 ps) of the output(s) being used which, while not
being catastrophic to most designs, will mean a loss of skew margin.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING
DIAGRAMS
MC10E111FN
AWLYYWW
PLCC鈥?8
FN SUFFIX
CASE 776
28 1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
MC100E111FN
AWLYYWW
28 1
ORDERING INFORMATION
Device
MC10E111FN
MC10E111FNR2
MC100E111FN
MC100E111FNR2
Package
PLCC鈥?8
PLCC鈥?8
PLCC鈥?8
PLCC鈥?8
Shipping
37 Units/Rail
500 Units/Reel
37 Units/Rail
500 Units/Reel
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Guaranteed Skew Spec
Differential Design
V
BB
Output
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 鈥?.2 V to 鈥?.7 V
鈥?/div>
Internal Input Pulldown Resistors
鈥?/div>
ESD Protection: > 3 KV HBM
鈥?/div>
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
鈥?/div>
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
鈥?/div>
Flammability Rating: UL鈥?4 code V鈥? @ 1/8鈥?
Oxygen Index 28 to 34
鈥?/div>
Transistor Count = 178 devices
漏
Semiconductor Components Industries, LLC, 2001
1
January, 2001 鈥?Rev. 5
Publication Order Number:
MC10E111/D
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