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VG3617161ET-8 Datasheet

  • VG3617161ET-8

  • CMOS Synchronous Dynamic RAM

  • 69頁

  • VML

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Description
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
鈥?Single 3.3V +/- 0.3V power supply
鈥?Clock frequency:166MHz, 143MHz, 125MHz
鈥?Fully synchronous with all signals referenced to a positive clock edge
鈥?Programmable CAS Iatency (2,3)
鈥?Programmable burst length (1,2,4,8,& Full page)
鈥?Programmable wrap sequence (Sequential/Interleave)
鈥?Automatic precharge and controlled precharge
鈥?Auto refresh and self refresh modes
鈥?Dual internal banks controlled by A11(Bank select)
鈥?Simultaneous and independent two bank operation
鈥?I/O level : LVTTL interface
鈥?Random column access in every cycle
鈥?X16 organization
鈥?Byte control by LDQM and UDQM
鈥?4096 refresh cycles/64ms
鈥?Burst termination by burst stop and precharge command
Document:1G5-0189
Rev.1
Page 1

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