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VG36128801A Datasheet

  • VG36128801A

  • CMOS Synchronous Dynamic RAM

  • 69頁

  • VML

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VIS
Description
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank,
4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
鈥?Single 3.3V (
鹵
0.3V) power supply
鈥?High speed clock cycle time : 7.5ns/10ns
鈥?Fully synchronous with all signals referenced to a positive clock edge
鈥?Programmable CAS Iatency (2,3)
鈥?Programmable burst length (1,2,4,8,& Full page)
鈥?Programmable wrap sequence (Sequential/Interleave)
鈥?Automatic precharge and controlled precharge
鈥?Auto refresh and self refresh modes
鈥?Quad Internal banks controlled by BA0 & BA1 (Bank select)
鈥?Each Bank can be operated simultaneously and independently
鈥?I/O level : LVTTL compatible
鈥?Random column access in every cycle
鈥?x4, x8, x16 organization
鈥?Input/Output controlled by DQM ( LDQM, UDQM )
鈥?4,096 refresh cycles/64ms
鈥?Burst termination by burst stop and precharge command
鈥?Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0154
Rev.1
Page 1

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