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VG26VS17405FJ Datasheet

  • VG26VS17405FJ

  • 4,194,304 x 4 - Bit CMOS Dynamic RAM

  • 245.42KB

  • 27頁

  • VML

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VIS
Description
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. A new refresh feature called 鈥渟elf-refresh鈥?is supported and very slow CBR
cycles are being performed. lt is packaged in JEDEC standard 26/24-pin plastic SOJ.
Features
鈥?Single 5V(
鹵
10 %) or 3.3V(+10%,-5%) only power supply
鈥?High speed t
RAC
acess time: 50/60ns
鈥?Low power dissipation
- Active wode : 5V version 660/605 mW (Mas)
3.3V version 432/396 mW (Mas)
- Standby mode: 5V version 1.375 mW (Mas)
3.3V version 0.54 mW (Mas)
鈥?Extended - data - out(EDO) page mode access
鈥?I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
鈥?2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
鈥?4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Document:1G5-0162
Rev.1
Page 1

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