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VDSL5100 Datasheet

  • VDSL5100

  • 5th Generation Single-port Standard VDSL Chip Set

  • 2頁

  • INFINEON   INFINEON

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P
RODUCT
B
RIEF
Infineon鈥檚 VDSL5100 standard VDSL single port
chip set provides highly flexible solutions for
Ethernet and ATM applications over VDSL.
Access system designers鈥?requirements are
addressed by providing flexible band allocation
plans and PSDs. VDSL5100 also supports Band 0
to extend VDSL services up to 4 km (13,200 ft.)
over ADSL frequencies.
Infineon鈥檚 VDSL5100 chip set uses Frequency
Division Multiplexing (FDM) and Quadrature
Amplitude Modulation (QAM) to provide simple,
low-cost, low-power, and very robust operation.
Infineon鈥檚 VDSL5100 is designed to coexist with
voice, ISDN, and other xDSL technologies in the
same bundle.
With Infineon鈥檚 software configurable VDSL5100
chip set, system vendors can use a single design
to support a wide variety of transport protocols.
The VDSL5100 is ideal for universal DSLAM
linecards and CPE designs.
Applications
s
Customer Premises Equipment
(CPE)
s
DSLAM and residential gateways
s
Ethernet and ATM over VDSL for
last mile access solutions
s
Fiber and broadband wireless
extension over copper wire
s
Multiple Dwelling/Tenant Units
(MDU/MTU) networking
s
LAN extentsions up to 1,200 m
(4,000 ft.)
s
Upgrades of HDSL, SDSL and
ADSL systems
Features
s
Ethernet and ATM single port chip
set
s
Highly integrated, standard
compliant, VDSL QAM transport
modem
s
Low power consumption
s
T1E1.4, ETSI, and ITU-T
compliant high speed VDSL PHY
applications
s
Ethernet transfer over AAL5 and
RFC 2684
s
Frequency Division Duplexing
(FDD)
2, 3, or 4-band operation,
including Band 0
VDSL5100
Interfaces
s
s
MII/SMII/SS-SMII/RMII
compliant with the 802.3 Ethernet
specification
ATM UTOPIA Level 1 and
Level 2, 8-bit, 33 MHz
32-channel Pulse Code
Modulation (PCM), maximum
2 Mbit/s over the fast channel
MII serial management interface
to access all internal registers
External parallel host port
Serial UART interface to a
standard serial terminal
EEPROM interface via IIC
IEEE 1149.1 JTAG test port
s
Dual latency support with built-in
interleaver memory
Power Back Off
Embedded crystal oscillator
(DCXO) for timing recovery
Spectral allocation allows noise
free operation with xDSL, ISDN,
TCM-ISDN and digital PBX
Versatile and completely flexible
band allocations
Backward compatibility with
Infineon鈥檚 legacy chip sets
s
s
s
s
s
s
s
s
s
s
s
s
Performance
s
Asymmetric DS/US data rates of
70/40 Mbit/s and Symmetric data
rates up to 50 Mbit/s
Asymmetric DS/US data rates of
4/0.6 Mbit/s up to 4 km (13,200 ft.)
Power Requirements
s
s
s
3.3 V and 1.2 V for the PEF 22818
1.8 V for the PEF 22815
鹵5 V for the PEF 22810
s
VDSL5100
5th Generation Single-port Standard VDSL Chip Set
VDSL5100-D, PEF 22818
4bVDSL-A, PEF 22815
VDSL-L, PEF 22810
N e v e r
s t o p
t h i n k i n g .

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