Product Data Sheet
VDSGLD @ 38.88 MHz
Voltage Controlled Crystal Oscillator
Pin Information
Table 1. Pin Function
Pin
Symbol
1
2
3
4
5
6
V
C
Tri-State
GND
Output
TTL/CMOS
V
cc
Function
Control Voltage
TTL logic low disables output
TTL logic high enables output waveform
Case Ground
Output waveform
TTL logic low for CMOS optimized symmetry
TTL logic high or no connection for TTL optimized symmetry
Power Supply Voltage (3.3 V
鹵10%)
Performance Characteristics
Table 2. Electrical Performance
Parameter
Nominal Output Frequency
Supply Voltage
1
Operating Temperature Range
Supply Current
Output Voltage Levels
Output Logic High
Output Logic Low
Output Rise/Fall Time
2
Output Duty Cycle or Symmetry
3
Absolute Pull Range, Vc = 1.0 to 2.0 V
Absolute Pull Range, Vc = 0.3 to 3.0 V
Initial Accuracy (Vc = 1.65V @25擄C)
Linearity
Start up time (To reach 90% of final amplitude)
Control Voltage Input Impedance
Control Voltage Leakage Current
Control Voltage Bandwidth (-3 dB, V
C
= 1.65 V)
Output Load
1. A 0.1
碌F
low frequency tantalum bypass capacitor in parallel with a 0.01
碌F
high frequency ceramic capacitor is recommended.
2. Figure 1 defines these parameters. Figure 2 illustrates the operating conditions.
3. Duty cycle is defined as (on time/period) per Figure 1.
4. Maxixmum control Voltage Leakage Current is by design.
Symbol
f
0
V
DD
T
O
I
DD
V
OH
V
OL
T
R
/T
F
D
APR
APR
Minimum
-
2.97
-40
Typical
38.88
3.3
Maximum
-
3.63
85
20
Units
MHz
V
擄C
mA
V
0.9*V
DD
0.1*V
DD
5
45
鹵5
鹵50
-20
+20
20
10
10
100
50
55
nS
%
ppm
ppm
ppm
%
ms
M鈩?/div>
nA
KHz
BW
10
15
pf
T
R
Voh
T
F
+
-
I
DD
6
V
DD
2
5
3
650鈩?/div>
Vs
Vol
.
1碌F
.01碌F
I
C
1
+
-
4
15pF
1.8k
On Time
Period
V
C
Figure 1. Output Waveform
Figure 2. Output Test Conditions (25鹵5擄C)
鹵
1/2
Vectron International
鈥?/div>
267 Lowell Road, Hudson, NH 03051
鈥?/div>
Tel: 1-88-VECTRON-1鈥?http://www.vectron.com
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