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V62C318256 Datasheet

  • V62C318256

  • 2.7 VOLT 32K X 8 STATIC RAM

  • 12頁(yè)

  • MOSEL

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MOSEL VITELIC
V62C318256
2.7 VOLT 32K X 8 STATIC RAM
PRELIMINARY
Features
I
High-speed: 35, 70 ns
I
Ultra low DC operating current of 2mA (max.)
I
Low Power Dissipation:
鈥?TTL Standby: 0.5 mA (Max.)
鈥?CMOS Standby: 10
碌
A (Max.)
I
Fully static operation
I
All inputs and outputs directly compatible
I
Three state outputs
I
Ultra low data retention current (V
CC
= 2V)
I
Extended operating voltage: 2.7V鈥?.6V
I
Packages
鈥?28-pin TSOP (Standard)
鈥?28-pin 300 mil SOP (450 mil pin-to-pin)
Description
The V62C318256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC鈥檚 high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A
0
Row
Decoder
512 x 512
Memory Array
V
CC
GND
A
8
I/O
0
Input
Data
Circuit
I/O
7
A
9
CE
OE
WE
Column I/O
Column Decoder
A
14
Control
Circuit
318256 01
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
鈥?0
擄
C to +85
擄
C
Package Outline
T
鈥?/div>
鈥?/div>
F
鈥?/div>
鈥?/div>
Access Time (ns)
35
鈥?/div>
鈥?/div>
70
鈥?/div>
L
鈥?/div>
Power
LL
鈥?/div>
鈥?/div>
Temperature
Mark
Blank
I
V62C318256 Rev. 1.7 July 2001
1

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