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V61C518256 Datasheet

  • V61C518256

  • 32K X 8 HIGH SPEED STATIC RAM

  • 61.04KB

  • 12頁

  • MOSEL

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MOSEL VITELIC
V61C518256
32K X 8 HIGH SPEED
STATIC RAM
Description
PRELIMINARY
Features
s
High-speed: 10, 12, 15 ns
s
Low Power Dissipation:
鈥?CMOS Standby: 0.5 mA (Max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 2V)
s
Single 5V
鹵
10% Power Supply
s
Packages
鈥?28-pin TSOP (Standard)
鈥?28-pin 300 mil SOJ
The V61C518256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC鈥檚 high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A
0
A
1
A
6
A
10
A
13
A
14
I/O
0
Input
Data
Circuit
I/O
7
A
2
CE
OE
WE
A
5
A
11
A
12
Row
Decoder
512 x 512
Memory Array
V
CC
GND
Column I/O
Column Decoder
Control
Circuit
518256-01
Device Usage Chart
Operating
Temperature
Range
0
擄C
to 70
擄C
Package Outline
T
鈥?/div>
N
鈥?/div>
R
鈥?/div>
10
鈥?/div>
Access Time (ns)
12
鈥?/div>
15
鈥?/div>
Temperature
Mark
Blank
V61C518256 Rev. 0.3 July 1998
1

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