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V61C5181024 Datasheet

  • V61C5181024

  • 128K X 8 HIGH SPEED STATIC RAM

  • 64.26KB

  • 12頁

  • MOSEL

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MOSEL VITELIC
V61C5181024
128K X 8 HIGH SPEED
STATIC RAM
PRELIMINARY
Features
s
s
s
s
s
s
s
High-speed: 10, 12, 15 ns
Fully static operation
All inputs and outputs directly TTL compatible
Three state outputs
Low data retention current (V
CC
= 2V)
Single 5V
鹵
10% Power Supply
Low CMOS Standby current of 5 mA max
s
Packages
鈥?32-pin TSOP
鈥?32-pin 300 mil SOJ
Description
The V61C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing
with common system bus structures. The
V61C5181024 is available in 32-pin SOJ, PDIP and
TSOP.
Functional Block Diagram
A
0
Row
Decoder
Memory Array
V
CC
GND
A
8
I/O
0
Input
Data
Circuit
I/O
7
A
9
CE
1
CE
2
OE
WE
Column I/O
Column Decoder
A
16
Control
Circuit
5181024 01
Device Usage Chart
Operating
Temperature
Range
0
擄C
to 70
擄C
Package Outline
T
鈥?/div>
R
鈥?/div>
10
鈥?/div>
Access Time (ns)
12
鈥?/div>
15
鈥?/div>
Temperature
Mark
Blank
V61C5181024 Rev. 1.1 July 1998
1

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