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V58C365164S Datasheet

  • V58C365164S

  • 64 Mbit DDR SDRAM 4M X 16, 3.3VOLT

  • 44頁

  • MOSEL

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V58C365164S
64 Mbit DDR SDRAM
4M X 16, 3.3VOLT
PRELIMINARY
CILETIV LESO M
36
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK2
)
275 MHz
3.6 ns
4.3ns
5.4ns
4
250 MHz
4 ns
4.8 ns
6 ns
5
200 MHz
5 ns
6 ns
7.5 ns
Features
鈻?/div>
4 banks x 1Mbit x 16 organization
鈻?/div>
High speed data transfer rates with system
frequency up to 275 MHz
鈻?/div>
Data Mask for Write Control (DM)
鈻?/div>
Four Banks controlled by BA0 & BA1
鈻?/div>
Programmable CAS Latency: 2, 2.5, 3
鈻?/div>
Programmable Wrap Sequence: Sequential
or Interleave
鈻?/div>
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
鈻?/div>
Automatic and Controlled Precharge Command
鈻?/div>
Suspend Mode and Power Down Mode
鈻?/div>
Auto Refresh and Self Refresh
鈻?/div>
Refresh Interval: 4096 cycles/64 ms
鈻?/div>
Available in 66-pin 400 mil TSOP-II
鈻?/div>
SSTL-2 Compatible I/Os
鈻?/div>
Double Data Rate (DDR)
鈻?/div>
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
鈻?/div>
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
鈻?/div>
Differential clock inputs CLK and CLK
鈻?/div>
Power supply 3.3V 鹵 0.3V
鈻?/div>
VDDQ (I/O) power supply 2.5 + 0.2V
Description
The V58C365164S is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C365164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0擄C to 70擄C
Package Outline
JEDEC 66 TSOP II
鈥?/div>
CLK Cycle Time (ns)
-36
鈥?/div>
Power
Std.
鈥?/div>
-4
鈥?/div>
-5
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V58C365164S Rev. 1.7 March 2002
1

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