V58C3643204SAT
HIGH PERFORMANCE
3.3 VOLT 2M X 32 DDR SDRAM
4 X 512K X 32
PRELIMINARY
CILETIV LESOM
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
45
225MHz
50
200 MHz
5 ns
55
183 MHz
5.5 ns
60
166 MHz
6 ns
4.5 ns
Features
s
4 banks x 512K x 32 organization
s
High speed data transfer rates with system
frequency up to 225 MHz
s
Data Mask for Write Control (DM)
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 3, 4
s
Programmable Wrap Sequence: Sequential
or Interleave
s
Programmable Burst Length:
2, 4, 8 full page for Sequential Type
2, 4, 8 full page for Interleave Type
s
Automatic and Controlled Precharge Command
s
Suspend Mode and Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 2048 cycles/16ms
s
Available in 100-pin TQFP
s
SSTL-2 Compatible I/Os
s
Double Data Rate (DDR)
s
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
s
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
s
Differential clock inputs CLK and CLK
s
Power Supply 3.3V 鹵 0.3V
Description
The V58C3643204SAT is a four bank DDR
DRAM organized as 4 banks x 512K x 32. The
V58C3643204SAT achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0擄C to 70擄C
Package Outline
100-pin TQFP
鈥?/div>
CLK Cycle Time (ns)
-45
鈥?/div>
Power
-60
鈥?/div>
-50
鈥?/div>
-55
鈥?/div>
Std.
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V58C3643204SAT Rev. 1.4 August 2001
1
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