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V54C365804VC Datasheet

  • V54C365804VC

  • HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS...

  • 54頁

  • MOSEL

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MOSEL VITELIC
V54C365804VC
HIGH PERFORMANCE 143/133/125 MHz
3.3 VOLT 8M X 8 SYNCHRONOUS DRAM
4 BANKS X 2Mbit X 8
PRELIMINARY
7
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
143MHz
7 ns
5.4 ns
5.5 ns
75
133MHz
7.5 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
8
125 MHz
8 ns
7 ns
7 ns
Features
s
4 banks x 2Mbit x 8 organization
s
High speed data transfer rates up to 143 MHz
s
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s
Single Pulsed RAS Interface
s
Data Mask for Read/Write Control
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 2, 3
s
Programmable Wrap Sequence: Sequential
or Interleave
s
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s
Multiple Burst Read with Single Write Operation
s
Automatic and Controlled Precharge Command
s
Random Column Address every CLK (1-N Rule)
s
Suspend Mode and Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 54 Pin 400 mil TSOP-II
s
LVTTL Interface
s
Single +3.3 V
鹵
0.3 V Power Supply
Description
The V54C365804VC is a four bank Synchronous
DRAM organized as 4 banks x 2Mbit x 8. The
V54C365804VC achieves high speed data transfer
rates up to 143 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
T
鈥?/div>
Access Time (ns)
7
鈥?/div>
Power
8
鈥?/div>
75
鈥?/div>
8PC
鈥?/div>
Std.
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V54C365804VC Rev. 0.6 September 1999
1

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