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V54C3256164VBUT Datasheet

  • V54C3256164VBUT

  • LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSO...

  • 45頁

  • MOSEL

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V54C3256164VBUC/T
LOW POWER 256Mbit SDRAM
3.3 VOLT, 54-BALL SOC BGA
54-PIN TSOPII 16M X 16
PRELIMINARY
CILETIV LESO M
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
鈻?/div>
4 banks x 4Mbit x 16 organization
鈻?/div>
High speed data transfer rates up to 166 MHz
鈻?/div>
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
鈻?/div>
Single Pulsed RAS Interface
鈻?/div>
Data Mask for Read/Write Control
鈻?/div>
Four Banks controlled by BA0 & BA1
鈻?/div>
Programmable CAS Latency: 2, 3
鈻?/div>
Programmable Wrap Sequence: Sequential or
Interleave
鈻?/div>
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
鈻?/div>
Multiple Burst Read with Single Write Operation
鈻?/div>
Automatic and Controlled Precharge Command
鈻?/div>
Random Column Address every CLK (1-N Rule)
鈻?/div>
Power Down Mode
鈻?/div>
Auto Refresh and Self Refresh
鈻?/div>
Refresh Interval: 8192 cycles/64 ms
鈻?/div>
Available in 54-Ball SOC BGA/ 54-Pin TSOP II
鈻?/div>
LVTTL Interface
鈻?/div>
Single +3.3 V
鹵0.3
V Power Supply
鈻?/div>
Low Power Self Refresh Current
鈻?/div>
L-version 1.0mA
鈻?/div>
U-version 0.6mA
Description
The V54C3256164VBUC/T is a low power four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16. The V54C3256164VBUC/T achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
The V54C3256164VBUC/T is ideally suited for
high performance, low power systems such as
PDA, mobile phone, DSC, and other battery backup
applications.
Device Usage Chart
Operating
Temperature
Range
0擄C to 70擄C
Package Out-
line
C/T
鈥?/div>
Access Time (ns)
6
鈥?/div>
Power
8PC
鈥?/div>
7PC
鈥?/div>
7
鈥?/div>
Std.
鈥?/div>
L
鈥?/div>
U
鈥?/div>
T
鈥?/div>
Temperature
Mark
Blank
V54C3256164VBUC/T Rev. 1.1 February 2003
1

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