音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

V54C3128 Datasheet

  • V54C3128

  • 128Mbit SDRAM 3.3 VOLT, BGA PACKAGE

  • 45頁

  • MOSEL

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
6
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
166 MHz
6 ns
5.4 ns
5.4 ns
PRELIMINARY
s
s
s
s
s
s
CILETIV LESOM
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
Features
s
s
s
s
s
4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 60 Pin WBGA
LVTTL Interface
Single +3.3 V
鹵0.3
V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
s
s
s
s
s
s
s
s
s
Device Usage Chart
Operating
Temperature
Range
0擄C to 70擄C
Package Outline
B
鈥?/div>
Access Time (ns)
6
鈥?/div>
Power
8PC
鈥?/div>
7PC
鈥?/div>
7
鈥?/div>
Std.
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
1

V54C3128相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！