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Wide clock frequency range from 20 MHz to 85 MHz
Spread spectrum compatible
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
Red, Green, Blue
HSYNC
VSYNC
DATA ENABLE
CONTROL
TxOUT2-
R_FB
PWRDWN
CLOCK
PLL
TxCLKOUT-
TxOUT3+
TxOUT3-
TxCLKOUT+
TTL to
LVDS
TxOUT1-
TxOUT2+
24
TxOUT0+
TxOUT0-
TxOUT1+
56-pin TSSOP
V385 Datasheet
1
3/30/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s 鈥?5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 鈥?t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 鈥?ww w.i c s t . c o m