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V350EPC-33 Datasheet

  • V350EPC-33

  • BUS CONTROLLER

  • 18頁

  • ETC

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V350EPC
Rev. A0
LOCAL BUS TO PCI BRIDGE
FOR MULTIPLEXED A/D PROCESSORS
鈥?Glueless interface to Intel鈥檚 i960Jx and IBM鈥檚
PowerPC
TM
401Gx processors
鈥?Configurable for primary master, bus master or
target operation.
鈥?Type 0 and type 1 configuration cycles.
鈥?Up to 1Kbyte burst access on PCI or local.
鈥?Large, 640-byte FIFOs using V3鈥檚 unique
D
YNAMIC
B
ANDWIDTH
A
LLOCATION
鈩?/div>
architecture
鈥?64-byte read FIFO per aperture.
鈥?Enhanced support for 8/16-bit local bus devices
with programmable region sizes.
鈥?3.3 volt support
鈥?Dual bi-directional address space remapping
鈥?Fully compliant with PCI 2.1 specification
V350EPC is a high-performance and low-cost
generic solution for interfacing both 32-bit and
16-bit multiplexed local bus applications to the
PCI bus. V350EPC directly connects to i960Jx or
i960Sx processors without any glue logic.
Minimal glue logic is required for high-
performance interfacing to other multiplexed
processors like Motorola ColdFire鈩?
V350EPC is the second generation of V3鈥檚 I
2
O
ready PCI bridges - fully backward compatible
with both V961PBC and V960PBC Rev B2
devices - and is supporting powerful features like
Hot Swap and DMA chaining. The PCI bus can
be run at the full 33MHz frequency, independent
of local bus clock rate. The overall throughput of
the system is dramatically improved by
increasing the FIFO depths and utilizing the
unique
D
Y N A M I C
B
A N D W I D T H
A
L L O C A T I O N
鈩?/div>
鈥?On-the-fly byte order (endian) conversion
鈥?I
2
O ATU and messaging unit including
hardware controlled circular queues
鈥?2 channel DMA controller plus multiprocessor
DMA chaining and demand mode DMA
鈥?Hot swapping capability
鈥?16 8-bit bi-directional mailbox registers with
doorbell interrupts
鈥?Flexible PCI and local interrupt management
鈥?Optional power-on serial EEPROM initialization
鈥?33MHz and 40MHz local bus versions
鈥?Industrials temperature grade -40 to +85鈥機
鈥?Low cost 160-pin EIAJ PQFP package
architecture.
Access to the PCI bus can be performed through
two programmable address apertures. Two more
apertures are provided for PCI-to-local bus
accesses. There are 64-bytes of read FIFOs in
each direction, 32-byte dedicated for each
aperture .
Two high-performance DMA channels with
chaining and demand mode capabilities provide
a powerful data transfer engine for bulk data
transfers. Mailbox registers and flexible PCI
interrupt controllers are also included to provide
a simple mechanism to emulate PCI device
control ports. The part is available in 160-pin low
cost PQFP packages in 33MHz and 40MHz
versions.
i960Jx
CPU
V96BMC
MEMORY
CONTROL
D
R
A
M
ROM
TYPICAL APPLICATION
V350EPC
LOCAL TO
PCI BRIDGE
PCI SLOT or EDGE CONNECTOR
PCI
PERIPHERAL
Copyright 漏 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
1
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V350EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.

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