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UTI760A RTS Remote Terminal for Stores

F

EATURES

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Complete MIL-STD-1760A Notice I through III

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remote terminal interface

1K x 16 of on-chip static RAM for message data,

completely accessible to host

Self-test capability, including continuous loop-back

compare

Programmable memory mapping via pointers for

ef鏗乧ient use of internal memory, including buffering

multiple messages per subaddress

RT-RT Terminal Address Compare

Command word stored with incoming data for

enhanced data management

User selectable RAM Busy (RBUSY) signal for slow

or fast processor interfacing

Full military operating temperature range, -55擄C to

+125擄C, screened to the speci鏗乧 test methods listed in

脣

Table I of MIL-STD-883, Method 5004, Class B, also

Standard Military Drawing available

Available in 68-pin pingrid array package

I

NTRODUCTION

The UT1760A RTS is a monolithic CMOS VLSI solution

to the requirements of the dual-redundant MIL-STD-1553B

interface as speci鏗乪d by MIL-STD-1760A. Designed to

reduce cost and space in the mission stores interface, the

RTS integrates the remote terminal logic with a user-

con鏗乬ured 1K x 16 static RAM. In addition, the RTS has a

鏗俥xible subsystem interface to permit use with most

processors or controllers.

The RTS provides all protocol, data handling, error

checking, and memory control functions, as well as

comprehensive self-test capabilities. The RTS鈥檚 memory

meets all of a mission store鈥檚 message storage needs through

user-de鏗乶ed memory mapping. This memory-mapped

architecture allows multiple message buffering at

MCSA(4:0)

MODE CODE/

SUBADDRESS

OUTPUT MULTIPLEXING AND

SELF-TEST WRAPAROUND LOGIC

RTA(4:0)

REMOTE TERMINAL

ADDRESS

CONTROL

INPUTS

OUT

STATUS

OUTPUTS

DECODER

COMMAND

RECOGNITION

CONTROL AND

ERROR LOGIC

1K X 16 RAM

ADDR(9:0)

MUX

ENCODER

PTR REGISTER

CLOCK AND RESET 12MHz

LOGIC

RESET

2MHz

Figure 1. UT1760A RTS Functional Block Diagram

IN

OUT

DECODER

IN

DATA(15:0)

RTS-1

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