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UT61L512 Datasheet

  • UT61L512

  • ASYNCHRONOUS STATIC RAM- High Speed

  • 10頁

  • ETC

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UTRON
Rev 1.2
UT61L512
64K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The UT61L512 is a 524,288-bit high-speed
CMOS static random access memory organized
as 524,288 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61L512 is designed for high-speed
system applications. It is particularly suited for
use in high-density high-speed system
applications.
The UT61L512 operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
FEATURES
Fast access time : 10/12/15 ns (max.)
Low operating power consumption :
60 mA (typical)
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 32-pin 300 mil SOJ
32-pin 8mmx20mm TSOP-I
FUNCTIONAL BLOCK DIAGRAM
A15
A13
A14
A12
A7
A6
A5
A4
A8
ROW
DECODER
PIN CONFIGURATION
.
.
.
MEMORY ARRAY
512 ROWS X 1024 COLUMNS
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
VSS
NC
A14
A12
A7
A6
A13
A8
A9
A11
OE
UT61L512
.
I/O1
.
.
A5
A4
A3
.
.
.
I/O8
CE1
.
.
.
I/O
CONTROL
.
.
.
COLUMN I/O
COLUMN DECODER
A2
A1
A0
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
CE
2
WE
OE
LOGIC
CONTROL
A10 A11 A9 A3 A2 A1 A0
I/O1
I/O2
I/O3
Vss
PIN DESCRIPTION
SOJ
SYMBOL
A0 - A15
I/O1 - I/O8
CE1 ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable 1, 2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
1
2
3
4
5
32
31
30
29
28
27
26
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
OE
A10
WE
CE2
A15
Vcc
NC
NC
A14
A12
A7
A6
A5
A4
6
7
8
9
10
11
12
13
14
15
16
UT61L512
25
24
23
22
21
20
19
18
17
TSOP-1
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80024
1

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