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UT52L1616 Datasheet

  • UT52L1616

  • 1Mx16(16M) SDRAM

  • 36頁

  • ETC

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UTRON
Preliminary Rev. 0.91
UT52L1616
1M
X 16 BIT SDRAM
FEATURES
PC100 compliant functionality and performance.
JEDEC standard 3.3 V
鹵
10% power supply.
LVTTL compatible inputs and outputs.
All inputs are sampled on positive edge of
system clock.
Dual Banks for hidden row access/precharge.
Internal pipeline operation, column addresses
can be changed every cycle.
DQM for masking.
MRS cycle with address key programmability
for:
- CAS latency ( 2 , 3 )
- Burst Length ( 1 , 2 , 4 , 8 or full page)
- Burst Type ( Sequential & Interleave )
Auto Precharge and Auto Refresh modes.
Self Refresh Mode.
64ms , 4096 cycle refresh ( 15.6 us/row )
50鈥損in 400 mil plastic TSOP (type II) package.
GENERAL DESCRIPTION
The UT52L1616 is a high-speed CMOS dynamic random-access memory containing 16,777,216 bits. It is
internally configured as a dual memory array (512K x 16) with a synchronous interface (all signals are registered
on the positive edge of the clock signal, CLK). Each of the two internal banks is organized with 2,048 rows and
with either 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence. Accesses begin with the registration of an
ACTIVATE command which will then be followed by a READ or WRITE command. The address bits registered
coincident with the ACTIVATE command are used to select the bank and row to be accessed (A11 selects the
bank, A0-10 selects the row). The address bits coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
The UT52L1616 uses an internal pipelined architecture to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every
clock cycle to achieve a high speed, fully random access. Precharging one bank while accessing the alternate
bank will hide the precharge cycles and provides seamless high-speed random access operation. The UT52L1616
is designed to comply with the Intel PC (66MHz) and Intel PC/100 (100MHz) specifications.
The UT52L1616 is designed to operate in 3.3V, low-power memory systems. An AUTO REFRESH mode is
provided along with a power saving Power-Down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst
data at a high data rate with automatic column-address generation, the ability to interleave between internal banks
in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
PRODUCT FAMILY
Part NO.
UT52L1616MC-7
UT52L1616MC-8
UT52L1616MC-10
Max Freq.
143MHZ
125MHZ
100MHZ
CL
3
3
3
tAC
5.5ns
6ns
7ns
Organization
2 banks脳512K bits脳16
Interface
LVTTL
Package
400 mil 50pin
TSOP II
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P90004
1

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