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Complies with jitter tolerance
and jitter transmit requirements
according to Telcordia GR-1244-
CORE and ITU-T G.825
Supports various clocking
modes based on external refer-
ence clocks, loop- and external
timing
Integrated bit error rate tester
(BERT) usable for multiple at-
speed diagnostic scenarios
Includes the XGXS, PCS, WIS,
and PMA sublayers of the OSI
protocol stack
Synchronization and de-skewing
of XAUI lanes
Integrated standard STS-192/
STM-64 SONET/SDH framer
according to GR-253-CORE,
ANSI T1. 105/416, ITU-T G.707.
Optionally maps/extracts
10 Gbit/s Ethernet packets into/
from the STS-192c/VC4-64c
payload or conveys them to the
serial interface directly
UPF 01002
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Performance monitoring accord-
ing to ANSI T1. 231
Various loop back modes for
system debugging
Provides access to E虜PROM via
I虜C interface according to XEN-
PAK requirements; automatic
E虜PROM download on power-up
Power-efficient design:
<1.3W @ 1.3V
Interfaces
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Full duplex, XFI compliant serial
CML line interface for data rates
between 9.95 and 10.5 Gbit/s
Quad serial Gbit/s XAUI interface
with data rates between 3.1 and
3.2 Gbit/s
MDIO interface
I虜C bus interface
XENPAK diagnostic interface
providing eight 12-bit ADCs and
four 10-bit DACs
IEEE 1149.1 JTAG boundary
scan interface
UPF 01002
TenGiPHY
錚?/div>
-W
N e v e r
s t o p
t h i n k i n g .
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10 Gigabit/s Ethernet Transceiver with OC-192c Framer and XA...
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10 Gigabit/s Ethernet Transceiver with OC-192c Framer and XA...
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10 Gigabit/s Transceiver with XAUI Interface
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