碌
PD98433
8-Port 10/100/1000 Mbps Ethernet
TM
Controller
Features
鈥?8-port 10/100/1000 Mbps Ethernet MAC compliant
with IEEE Std 802.3 1998 Edition
鈥?Standard GMII, MII and TBI I/F connected with PHY
devices
鈥?6K-byte receive FIFO and 6K-byte transmit FIFO for
Each Port
鈥?High performance data bus I/F
-
128-bit x 125 MHz x 2-port (Rx / Tx independent
uni-directional bus)
鈥?Full and half duplex for 10/100M operation, full duplex
for 1G operation
鈥?CPU Bus I/F : 32-bit x 62.5 MHz
鈥?Flow control compliant with IEEE Std 802.3 1998 Edition
鈥?8B/10B PCS function with auto negotiation for 1000
BASE-X
鈥?Address filtering & error packet discarding
鈥?Statistics counters per port (25 counters for Tx, 23
counters for Rx)
鈥?VLAN packet detection
鈥?JTAG support
鈥?0.25
碌
m CMOS process
鈥?2.5 V power supply, 3.3 V power supply for physical
layer interface
鈥?756-pin ABGA
Block Diagram
TBI
GMII
MII
x8
PORT #7
PORT #6
PORT #5
PORT #4
PORT #3
PORT #2
PORT #1
PORT #0
FIFO DATA
Common
Bus
Interface
............
FIFO
DATA
Bus
Tx FIFO
Rx FIFO
PCS
MII
Serial
Management
10/100/1000 Mbps
MAC
Register Set / Statistics Counter
CPU
Bus
CPU Bus
Interface
MII Management Interface
TEST
Port
JTAG
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14941EJ2V0PF00 (2nd edition)
Date Published December 2001 NS CP(K)
Printed in Japan
2000
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