碌
PD98412
ADVANCED ATM SWITCH LSI
TM
(NEASCOT-X15 )
Features
鈥?Conforms to the ATM FORUM UNI Version 3.1 & 4.0
鈥?All switching functions are integrated in a single chip
鈥?Non-blocking architecture with 1.5Gbps switching
capacity
鈥?Selectable UTOPIA Level2 data bit width
(8-bit x 4 ports, 8-bit x 2 ports + 16-bit x 1 port,
16-bit x 2 ports)
鈥?Some polling modes on UTOPIA Level2 Interface
鈥?Supporting 30 logical ports
鈥?Multiple speed (622Mbps, 155Mbps, 52Mbps,
25Mbps etc.)
鈥?Supports microprocessor port for signaling and OAM
cell processing
鈥?Up to 64K unicast virtual paths/virtual channels, up to 4K
multicast virtual paths/virtual channels
鈥?Shared buffer architecture that uses standard SRAMs
鈥?Cell buffer capacity up to 51.2K cells
鈥?Supports four QOS classes (CBR, VBR, ABR, UBR)
鈥?ABR traffic control (binary mode)
鈥?EPD(Early Packet Discard), PPD(Partial Packet Discard)
鈥?+ 3.3 V supply (+ 5 V tolerant inputs)
鈥?JTAG(IEEE 1149.1) support
鈥?576-pin tape BGA (40 x 40)
Block Diagram
Cell Buffer Memory
UTOPIA
receive
port 0
Input payload
separator
Cell buffer interface
Output payload
selector
UTOPIA
transmit
port 0
Input
header
separator
Queue
controller
Output
header
selector
UTOPIA
receive
port 2
Output port interface
Input port interface
UTOPIA
receive
port 1
UTOPIA
transmit
port 1
UTOPIA
transmit
port 2
Test
interface
UTOPIA
receive
port 3
Microprocessor
interface
HTT &
Control memory
interface
Output
arbiter
UTOPIA
transmit
port 3
Microprocessor
HTT & Control Memory
TEST
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14301EJ3V0PF00 (3rd edition)
Data Published November 2001 NS CP(K)
Printed in Japan
1999
1
2
