碌 P D 9 8 4 0 8 AT M P H Y S I C A L I N T E R FA C E
The 碌PD98408 incorporates six 25.6 Mbps ATM physical interface circuits (ports) into a single chip,
implementing complete physical layer functionality for transmission convergence (TC) and physical
media dependent (PMD) sublayer functions. Each port has an encoder/decoder, scrambler/descram-
bler, line equalizer, and clock recovery circuit for totally independent channel operation. This device
communicates with ATM layer devices using an integrated UTOPIA level 2 standard interface.
F E AT U R E S
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Complies with the ATM Forum Specifications for 25.6 Mbps ATM interface
Integrates six independent 25.6 Mbps physical interface circuits (ports)
Performs NRZI and 4B/5B encoding and decoding functions
Performs scrambler/descrambler, HEC generation/verification, and command byte
insertion/detection functions
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Integrates an independent clock recovery and line equalizer circuit for each port
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Supports Operation and Maintenance (OAM) functions, including the detection of
loss of signal (LOS), HEC errors, and 4B/5B code violations
BUS INTERFACE
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Uses the UTOPIA level 2 standard to ensure compatibility with multivendor ATM layer devices
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Provides a generic processor interface for device programming/option selection and status data
gathering
MEDIA INTERFACE
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Supports STP and UTP (categories 3, 4 and 5) cable types
GENERAL
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Provides diagnostic capabilities: loopback of receive data at the physical side and transmit data
at the UTOPIA interface, test signal generation and error insertion option
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Supports JTAG Boundary Scan
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Low-power CMOS technology (3.3-volt supply voltage)
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208-pin plastic QFP package
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