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UPD72872 Datasheet

  • UPD72872

  • UPD72872 Data Sheet | Data Sheet[11/2000]

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  • ETC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD72872
IEEE1394 1-CHIP OHCI HOST CONTROLLER
The
碌
PD72872 is the LSI which integrated OHCI-Link and PHY function into a single chip.
The
碌
PD72872 complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up
to 400 Mbps.
It makes design so compact for PC and PC card application.
FEATURES
鈥?Shrink from the
碌
PD72870A.
鈥?Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
鈥?Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)
鈥?Numbers of supported port (1, 2 ports) are selectable
鈥?Compliant with protocol enhancement as defined in P1394a draft 2.0
鈥?Modular 32-bit host interface compliant to PCI local bus specification Revision 2.2
鈥?Support PCI-Bus Power Management Interface Specification release 1.1
鈥?Modular 32-bit host interface compliant to Card Bus Specification
鈥?Cycle Master and Isochronous Resource Manager capable
鈥?32-bit CRC generation and checking for receive/transmit packets
鈥?4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
鈥?32-bit DMA channels for physical memory read/write
鈥?Clock generation by 24.576 MHz X鈥檛al
鈥?Internal control and operational registers direct-mapped to PCI configuration space
鈥?2-wire Serial EEPROM
TM
interface supported
鈥?Separate power supply Link and PHY
ORDERING INFORMATION
Part number
Package
120-pin plastic TQFP (Fine pitch) (14 x 14)
碌
PD72872GC-9EV
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14793EJ1V0DS00 (1st edition)
Date Published November 2000 NS CP (K)
Printed in Japan
The mark
#
shows major revised points.
2000

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