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UPD70F3017AY Datasheet

  • UPD70F3017AY

  • 32-BIT SINGLE-CHIP MICROCONTROLLER

  • 48頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
V850/SA1
32-BIT SINGLE-CHIP MICROCONTROLLER
TM
DESCRIPTION
The
碌
PD70F3015B, 70F3015BY, 70F3017A, and 70F3017AY are products with on-chip flash memory. Because
the devices can be programmed by the user on-board, they are ideal for the evaluation stages of system
development, small-scale production of a variety of products, and rapid development of new products.
The V850/SA1 provides a high-level cost performance ideal for applications ranging from low-power camcorders
and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone
systems (PHS).
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
V850/SA1 User's Manual Hardware:
TM
V850 Family User's Manual Architecture:
U12768E
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time:
58.8 ns (@ 17 MHz operation with main system
clock (f
XX
))
50 ns (@ 20 MHz operation with main system
clock (f
XX
))
30.5
碌
s (@ 32.768 kHz operation with subsystem
clock (f
XT
))
General-purpose registers: 32 bits
脳
32 registers
Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
Memory space:
16 MB linear address space
Memory block division function: 2 MB per block
Internal memory
鈥?/div>
Flash memory
128 KB (
碌
PD70F3015B, 70F3015BY)
256 KB (
碌
PD70F3017A, 70F3017AY)
鈥?/div>
RAM
4 KB (
碌
PD70F3015B, 70F3015BY)
8 KB (
碌
PD70F3017A, 70F3017AY)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
External bus interface: 16-bit data bus
Address bus: Separate output enabled
Interrupts and exceptions
External: 8, internal: 23, exceptions: 1
I/O lines Total: 85
Timer/counters
16-bit timer:
8-bit timer:
2 channels
4 channels
Watch timer: 1 channel
Watchdog timer: 1 channel
Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I C bus interface (
碌
PD70F3015BY, 70F3017AY)
2
A/D converter: 12 channels
DMA controller: 3 channels
RTP: 8 bits
脳
1 channel or 4 bits
脳
2 channels
Power-saving functions: HALT/IDLE/STOP modes
Packages: 100-pin plastic LQFP (14
脳
14 mm)
121-pin plastic FBGA (12
脳
12 mm)
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14527EJ3V0DS00 (3rd edition)
Date Published July 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
2000

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