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DATA SHEET

碌

PD703014A, 703014AY, 703015A,

703015AY, 703017A, 703017AY

V850/SA1

32-/16-BIT SINGLE-CHIP MICROCONTROLLER

TM

MOS INTEGRATED CIRCUIT

DESCRIPTION

The

碌

PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-

chip microcontrollers that include the CPU core of the V850 Family

TM

, and peripheral functions such as ROM/RAM,

timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.

In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1

includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,

all of which are instructions suited to digital servo control applications. As a real-time control system, this device

provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV

equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).

Detailed function descriptions are provided in the following user鈥檚 manuals. Be sure to read them before

designing.

V850/SA1 User鈥檚 Manual Hardware:

U12768E

TM

U10243E

V850 Family User鈥檚 Manual Architecture:

FEATURES

{

Number of instructions: 74

{

Minimum instruction execution time:

59 ns (@ 17 MHz operation with main system clock (f

XX

))

50 ns (@ 20 MHz operation with main system clock (f

XX

))

30.5

碌

s (@ 32.768 kHz operation with subsystem clock (f

XT

))

{

General-purpose registers: 32 bits

脳

32 registers

{

Instruction set:

Signed multiplication, saturation operations, 32-bit

shift instructions, bit manipulation instructions,

load/store instructions

{

Memory space:

16 MB linear address space

Memory block allocation function: 2 MB per block

{

External bus interface: 16-bit data bus

Address bus: Separate output enabled

{

Internal memory

Mask ROM: 64 KB (

碌

PD703014A, 703014AY)

128 KB (

碌

PD703015A, 703015AY)

256 KB (

碌

PD703017A, 703017AY)

RAM: 4 KB

(

碌

PD703014A, 703014AY, 703015A, 703015AY)

8 KB (

碌

PD703017A, 703017AY)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

{

Interrupts and exception

External: 8, internal: 23, exception: 1

{

I/O lines Total: 85

{

Timer/counters

16-bit timer:

8-bit timer:

2 channels

4 channels

{

Watch timer: 1 channel

{

Watchdog timer: 1 channel

{

Serial interface (SIO)

Asynchronous serial interface (UART)

Clocked serial interface (CSI)

I

2

C bus interface

(

碌

PD703014AY, 703015AY, 703017AY)

{

A/D converter: 12 channels

{

DMA controller: 3 channels

{

RTP: 8 bits

脳

1 channel or 4 bits

脳

2 channels

{

Power-saving functions: HALT/IDLE/STOP modes

{

Packages: 100-pin plastic LQFP (14

脳

14)

121-pin plastic FBGA (12

脳

12)

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. U14526EJ2V0DS00 (2nd edition)

Date Published September 2000 N CP(K)

Printed in Japan

The mark

shows major revised points.

漏

2000

next

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