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UPD488448FB-C80-45-DQ2 Datasheet

  • UPD488448FB-C80-45-DQ2

  • 128 M-bit Direct Rambus⑩ DRAM

  • 80頁

  • NEC   NEC

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DATA SHEET
碌
PD488448 for Rev. P
128 M-bit Direct Rambus鈩?DRAM
MOS INTEGRATED CIRCUIT
Description
The Direct Rambus DRAM (Direct RDRAM
鈩?/div>
) is a general purpose high-performance memory device suitable for
use in a broad range of applications including computer memory, graphics, video, and any other application where
high bandwidth and low latency are required.
The
碌
PD488448 is 128M-bit Direct Rambus DRAM (RDRAM
廬
), organized as 8M words by 16 bits.
The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using
conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers
at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data buses with independent row and column control
yield over 95% bus efficiency. The Direct RDRAM鈥檚 thirty-two banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power management, byte
masking.
The
碌
PD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and
mobile applications. Direct RDRAMs operate from a 2.5 volt supply.
Features
鈥?/div>
Highest sustained bandwidth per DRAM device
- 1.6 GB/s sustained data transfer rate
- Separate control and data buses for maximized efficiency
- Separate row and column control buses for easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
鈥?/div>
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
鈥?/div>
Advanced power management:
- Multiple low power states allows flexibility in power consumption versus time to transition to active state
- Power-down self-refresh
鈥?/div>
Overdrive current mode
鈥?/div>
Organization: 1 Kbyte pages and 32 banks, x 16
鈥?/div>
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
鈥?/div>
Package : 62-pin TAPE FBGA (
碌
BGA
廬
) and 62-pin PLASTIC FBGA (D BGA
鈩?/div>
(Die Dimension Ball Grid Array) )
2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14837EJ3V0DS00 (3rd edition)
Date Published August 2000 NS CP (K)
Printed in Japan
The mark
鈥?/div>
shows major revised points.
漏
2000

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