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UPD45D128164G5-C75-9LG Datasheet

  • UPD45D128164G5-C75-9LG

  • DDR Synchronous DRAM

  • 643.05KB

  • 80頁

  • ETC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD45D128442, 45D128842, 45D128164
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
Description
The
碌
PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic random-
access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
鈥?/div>
Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
鈥?/div>
Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
鈥?/div>
Quad internal banks operation
鈥?/div>
Possible to assert random column address in every clock cycle
鈥?/div>
Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
鈥?/div>
Automatic precharge and controlled precharge
鈥?/div>
CBR (Auto) refresh and self refresh
鈥?/div>
x4, x8, x16 organization
鈥?/div>
Byte write control (x4, x8) by DM
鈥?/div>
Byte write control (x16) by LDM and UDM
鈥?/div>
2.5 V
鹵
0.2 V Power supply for V
DD
鈥?/div>
2.5 V
鹵
0.2 V Power supply for V
DD
Q
鈥?/div>
Maximum clock frequency up to 133 MHz
鈥?/div>
SSTL_2 compatible with all signals
鈥?/div>
4,096 refresh cycles/64 ms
鈥?/div>
66-pin Plastic TSOP (II) (10.16 mm (400))
鈥?/div>
Burst termination by Precharge command and Burst stop command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0030N10 (1st edition)
(Previous No. M13852EJ3V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

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