DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD4564441-A75, 4564841-A75
64M-bit Synchronous DRAM, 133MHz
4-bank, LVTTL
Description
The
碌
PD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304
脳
4
脳
4 and 2,097,152
脳
8
脳
4 (word
脳
bit
脳
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin plastic TSOP (II).
Features
鈥?/div>
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
鈥?/div>
Pulsed interface
鈥?/div>
Possible to assert random column address in every cycle
鈥?/div>
Quad internal banks controlled by A12 and A13 (Bank Select)
鈥?/div>
Programmable Wrap sequence (Sequential / Interleave)
鈥?/div>
Programmable burst length (1, 2, 4, 8 and full page)
鈥?/div>
/CAS latency (3)
鈥?/div>
Automatic precharge and controlled precharge
鈥?/div>
CBR (auto) refresh and self refresh
鈥?脳4, 脳8
organization
鈥?/div>
Single 3.3 V
鹵
0.3 V power supply
鈥?/div>
LVTTL compatible inputs and outputs
鈥?/div>
4,096 refresh cycles / 64 ms
鈥?/div>
Burst termination by Burst stop command and Precharge command
Ordering Information
Part number
Organization
(word
脳
bit
脳
bank)
4M
脳
4
脳
4
2M
脳
8
脳
4
Clock frequency
MHz (MAX.)
133
Package
54-pin Plastic TSOP (II)
(10.16mm (400))
碌
PD4564441G5-A75-9JF
碌
PD4564841G5-A75-9JF
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13977EJ5V0DS00 (5th edition)
Date Published January 2000 NS CP (K)
Printed in Japan
The mark
鈥?/div>
shows major revised points.
漏
1998
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