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UPD4383362GF-A75 Datasheet

  • UPD4383362GF-A75

  • x36 Fast Synchronous SRAM

  • 163.44KB

  • 16頁(yè)

  • ETC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD4383362
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The
碌
PD4383362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using N-channel four-transistor memory cell.
The
碌
PD4383362 is suitable for applications which require synchronous operation, high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
碌
PD4383362 is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
鈥?/div>
Fully synchronous operation
鈥?/div>
HSTL Input / Output levels
鈥?/div>
鈥?/div>
Fast clock access time : 3.8 ns / 133 MHz
鈥?/div>
Asynchronous output enable control : /G
鈥?/div>
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
鈥?/div>
Common I/O using three-state outputs
鈥?/div>
Internally self-timed write cycle
鈥?/div>
Late write with 1 dead cycle between Read-Write
鈥?/div>
3.3 V (Chip) / 1.5 V (I/O) supply
鈥?/div>
100-pin plastic LQFP package, 14 mm x 20 mm
鈥?/div>
Sleep Mode : ZZ(Enables sleep mode, active high)
Ordering Information
Part number
Access time
3.8 ns
Clock frequency
133 MHz
Package
100-PIN PLASTIC LQFP (14 x 20)
鈥?/div>
碌
PD4383362GF-A75
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14438EJ3V0DS00 (3rd edition)
Date Published July 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
漏
1999

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