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UPD30700RS-200 Datasheet

  • UPD30700RS-200

  • Microprocessor

  • 265.15KB

  • 68頁

  • ETC

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DATA SHEET
碌
PD30700,30700L,30710
V
R
10000
TM
, V
R
12000
TM
64-BIT MICROPROCESSORS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
碌
PD30700 and 30700L (V
R
10000) and
碌
PD30710 (V
R
12000) are new members of NEC鈥檚 V
R
series
TM
RISC
(Reduced Instruction Set Computer) microprocessors. These new high-performance 64-bit microprocessors employ
a new RISC architecture developed by MIPS
TM
, ANDES
TM
architecture.
The V
R
10000 and V
R
12000 are designed to be used in high-performance computers and achieve considerably
higher processing speed through the employment of a super scalar pipeline.
Remark
ANDES: Architecture with Non-sequential Dynamic Execution Scheduling
The functions of these microprocessors are described in detail in the following manuals. Be sure to read these
manuals when designing systems.
V
R
10000, V
R
12000 User鈥檚 Manual
: U10278E
V
R
5000
TM
, V
R
10000 User鈥檚 Manual - Instruction : U12754E
FEATURES
鈥?/div>
MIPS 64-bit RISC architecture
鈥?/div>
High-speed operation processing
Super scalar pipeline executing five instructions in parallel
<V
R
10000>
鈥?14SPECint95, 23SPECfp95
<V
R
12000>
鈥?17SPECint95, 27SPECfp95
鈥?/div>
Operating frequency
<V
R
10000>
鈥?Internal: 250 MHz MAX.
鈥?External: 250 MHz MAX.
鈥?External/internal multiplication factor selectable from
1 to 4
<V
R
12000>
鈥?Internal: 300 MHz MAX.
鈥?External: 150 MHz MAX.
鈥?External/internal multiplication factor selectable from
2 to 10
鈥?/div>
Instruction
entries)
set upward-compatible with V
R
4000
TM
,
V
R
4200
TM
, and V
R
4400
TM
(conforms to MIPS-I/II/III/IV)
鈥?/div>
High-speed translation lookaside buffer (TLB) (64 double
鈥?/div>
Address space
Physical: 40 bits
Virtual: 44 bits
鈥?/div>
Multi-processor function
鈥?Up to four buses of cluster connection can be connected.
鈥?/div>
Floating-point unit (FPU)
鈥?/div>
Supply voltage
鈥?/div>
Primary cache memory (32K bytes for each of instruction <V
R
10000>
and data, 2-way set associative)
V
DD
= 3.3 V
鹵0.165
V (
碌
PD30700)
鈥?/div>
Secondary cache memory interface
鈥?128-bit secondary cache interface
鈥?SSRAM interface (V
R
10000: 250 MHz MAX., V
R
12000:
200 MHz MAX.)
鈥?Supports up to 16M bytes
V
DD
= 2.6 V
鹵0.1
V (
碌
PD30700L)
<V
R
12000>
V
DD
= 2.6 V
鹵0.1
V (
碌
PD30710)
Unless otherwise specified, the V
R
10000 is treated as the representative model throughout this document.
The information in this document is subject to change without notice.
Date No. U12703EJ1V0DS00 (1st edition)
Date Published June 1998 N CP(K)
Printed in Japan
1998
漏
MIPS Technologies Inc. 1998
漏

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