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UPD30550A Datasheet

  • UPD30550A

  • UPD30550A Data Sheet | Data Sheet[04/2003]

  • 28頁

  • ETC

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DATA SHEET
DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD30550A
V
R
5500A
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The
碌
PD30550A (V
R
5500A) is a member of the V
RTM
Series of RISC (Reduced Instruction Set Computer)
microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by
MIPS
TM
.
The V
R
5500A allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using
protocols compatible with the V
R
5000 Series and V
R
5432.
Detailed function descriptions are provided in the following user鈥檚 manual. Be sure to read the manual
before designing.
鈥?/div>
V
R
5500A User鈥檚 Manual (U16677E)
FEATURES
鈥?/div>
MIPS 64-bit RISC architecture
鈥?/div>
High-speed operation processing
鈥?/div>
Two-way superscalar super pipeline
鈥?/div>
300 MHz product:
400 MHz product:
(48 entries)
鈥?/div>
Address space
鈥?/div>
Physical:
鈥?/div>
Virtual:
36 bits (64-bit bus selected)
32 bits (32-bit bus selected)
40 bits (in 64-bit mode)
31 bits (in 32-bit mode)
鈥?/div>
On-chip floating-point unit (FPU)
鈥?/div>
Supports sum-of-products instructions
鈥?/div>
On-chip primary cache memory
(instruction/data: 32 KB each)
鈥?/div>
2-way set associative
鈥?/div>
Supports line lock feature
603 MIPS
804 MIPS
鈥?/div>
64-/32-bit address/data multiplexed bus
鈥?/div>
Bus width selectable during reset
鈥?/div>
Bus protocol compatibility with existing products
retained
鈥?/div>
Maximum operating frequency
鈥?/div>
300 MHz product: Internal 300 MHz, external 133
MHz
400 MHz product: Internal 400 MHz, external 133
MHz
鈥?/div>
External/internal multiplication factor selectable from
脳2
to
脳5.5
by increments of 0.5
鈥?/div>
Conforms to MIPS I, II, III, and IV instruction sets. Also
supports product-sum operation instruction, rotate
instruction, register scan instruction, and instruction for
low power mode.
鈥?/div>
Supports hardware debug function (N-Wire)
鈥?/div>
Supply voltage
Core block:
I/O block:
1.5 V
鹵5%
(300 MHz product)
1.6 to 1.7 V (400 MHz product)
3.3 V
鹵5%,
2.5 V
鹵5%
鈥?/div>
High-speed translation lookaside buffer (TLB)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U16678EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2003
2001

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