鈥?/div>
V
R
4100 Series
TM
Architecture User鈥檚 Manual (U15509E)
FEATURES
鈥?Employs 64-bit MIPS architecture
鈥?Conforms to MIPS III instruction set (deleting FPU,
LL, LLD, SC, and SCD instructions)
鈥?Optimized 5-stage pipeline
鈥?Supports MIPS16 instruction set
鈥?Supports high-speed product-sum operation
instructions
鈥?Supports four types of operating modes, enabling
more effective power-consumption management
鈥?Internal maximum operating frequency: 180/150 MHz
鈥?On-chip clock generator
鈥?Address space physical: 32 bits
virtual:
40 bits
Integrates 32 double-entry TLBs
鈥?High-capacity instruction/data separated cache
memories
Instruction: 32 KB
Data:
16 KB
鈥?Memory controller (ROM, synchronous DRAM
(SDRAM), and flash memory supported)
鈥?Supports PCI bus subset
鈥?4-channel DMA controller
鈥?Serial interface (NS16550 compatible)
鈥?On-chip clocked serial interface
鈥?IrDA interface for infrared communication
鈥?Debug serial interface
鈥?Power supply voltage:
V
DD
1 = 1.8 to 2.0 V (150 MHz model),
1.9 to 2.0 V (180 MHz model)
V
DD
3 = 3.0 to 3.6 V
鈥?Package: 224-pin fine-pitch FBGA
APPLICATIONS
鈥?/div>
Battery-driven portable information systems
鈥?/div>
Embedded controllers, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U15585EJ3V0DS00 (3rd edition)
Date Published December 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
next