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UPD23C64202LG5-XXX-9JH Datasheet

  • UPD23C64202LG5-XXX-9JH

  • x16 or x32 ROM (Mask Programmable)

  • 84頁

  • ETC

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DATA SHEET
碌
PD23C64202L
64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM
4M-WORD BY 16-BIT (WORD MODE) / 2M-WORD BY 32-BIT (DOUBLE WORD MODE)
MOS INTEGRATED CIRCUIT
Description
The
碌
PD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus.
The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode : 2,097,152
words by 32 bits).
The
碌
PD23C64202L is packed in 86-pin PLASTIC TSOP (II).
Features
鈥?/div>
Fully synchronous mask-ROM; all signals referenced to a positive clock edge
鈥?/div>
Word organization :
4,194,304 words by 16 bits (WORD mode)
2,097,152 words by 32 bits (DOUBLE WORD mode)
鈥?/div>
Operation frequency : up to 100 MHz
Operation supply
voltage
V
CC
Clock frequency
MHz
Access time from CLK
ns (MAX.)
Operating current
(Burst mode)
mA (MAX.)
150
Standby current
(CMOS level input)
碌
A (MAX.)
100
5
3.3 V
鹵
0.3 V
100
83
66
50
33
6
8
9
9
9
鈥?/div>
Programmable wrap type : Sequential or Interleave
鈥?/div>
Programmable burst length : 4, 8
鈥?/div>
Programmable /CAS latency : 3, 4, 5 or 6
鈥?/div>
Programmable /RAS latency : 1, 2
鈥?/div>
Burst termination by BURST STOP command
鈥?/div>
LVTTL compatible inputs and outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13945EJ5V0DS00 (5th edition)
Date Published August 2001 NS CP (K)
Printed in Japan
The mark
!
shows major revised points.
漏
1999

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