DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD178076,178078,178096,178098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
碌
PD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware
for digital tuning systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In
addition, the
碌
PD178076 and 178078 have an asynchronous serial interface (UART) mode, and the
碌
PD178096 and
178098 have an IEBus
TM
controller.
Moreover, a flash memory model, the
碌
PD178F098, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User鈥檚 Manuals:
碌
PD178078, 178098 Subseries User鈥檚 Manual : U12790E
78K/0 Series User鈥檚 Manual - Instruction
: U12326E
FEATURES
鈥?/div>
High-capacity ROM and RAM
Item Program Memory (ROM)
Part Number
Data Memory
Internal high-speed RAM Internal buffer RAM
48K bytes
60K bytes
1024 bytes
32 bytes
Internal extension RAM
1024 bytes
2048 bytes
碌
PD178076, 178096
鈥?/div>
Instruction cycle:
鈥?/div>
碌
PD178078, 178098
0.32
碌
s (with crystal resonator of f
X
= 6.3 MHz)
Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (UART mode:
碌
PD178076 and 178078
鈥?/div>
Hardware for PLL frequency synthesizer
phase comparator, charge pump
dual modulus prescaler, programmable divider,
鈥?/div>
Vectored interrupt sources
鈥?/div>
Supply voltage
鈥?/div>
碌
PD178076, 178078: 22
鈥?/div>
碌
PD178096, 178098: 21
only), IEBus controller (
碌
PD178096 and 178098
only), timers, frequency counter, power-ON clear
circuit
:V
DD
= 4.5 to 5.5 V (during PLL and CPU
operations)
:V
DD
= 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12885EJ3V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1997, 2000
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