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UPD178016 Datasheet

  • UPD178016

  • 8-BIT SINGLE-CHIP MICROCONTROLLER

  • 56頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD178004, 178006, 178016, 178018
8-BIT SINGLE-CHIP MICROCONTROLLER
The
碌
PD178004, 178006, 178016 and 178018 are 8-bit single-chip CMOS microcontrollers that incorporate
hardware for digital tuning systems.
The CPU uses the 78K/0 architecture and high-speed access to internal memory and control of peripheral
hardware are easy to implement. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial
interface, power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a
frequency counter.
The
碌
PD178P018, one-time PROM or EPROM versions which can be operated in the same supply voltage
range as for the mask ROM versions, and various development tools, are also available.
For more information on functions, refer to the following User鈥檚 Manuals. Be sure to read them when
designing.
碌
PD178018 Subseries User鈥檚 Manual: U11410E
78K/0 Series User鈥檚 Manual Instruction: IEU-1372
FEATURES
鈥?Internal high-capacity ROM and RAM
Items
Product Name
Program Memory
ROM
32 Kbytes
48 Kbytes
2048 bytes
60 Kbytes
Internal High-Speed RAM
1024 bytes
Data Memory
Buffer RAM
32 bytes
Internal Expanded RAM
Not provided
碌
PD178004
碌
PD178006
碌
PD178016
碌
PD178018
鈥?Instruction Cycle: 0.44
碌
s (4.5-MHz crystal oscillator used)
鈥?Large array of on-chip peripheral hardware
General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear
circuits.
鈥?On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
鈥?Vector Interrupts: 17
鈥?Supply Voltage: V
DD
= 4.5 to 5.5 V (during PLL operation)
V
DD
= 3.5 to 5.5 V (during CPU operation, when the system clock is f
X
/2 or lower)
V
DD
= 4.5 to 5.5 V (during CPU operation, when the system clock is f
X
)
The information in this document is subject to change without notice.
Document No. U11800EJ2V1DS00 (2nd Edition)
Date Published March 1997 N
Printed in Japan
The mark
*
shows major revised points.
漏
1997

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