鈥?/div>
CMOS level input (2.3 to 3.6 V)
384 outputs
Input of 6 bits (gray-scale data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
Logic power supply voltage (V
DD1
): 2.3 to 3.6 V
Driver power supply voltage (V
DD2
): 7.5 to 9.5 V
High-speed data transfer: f
CLK
= 65 MHz MAX. (internal data transfer speed when operating at V
DD1
= 2.7 V)
40 MHz MAX. (internal data transfer speed when operating at V
DD1
= 2.3 V)
Output dynamic range: V
SS2
+ 0.2 V to V
DD2
鈥?0.2 V
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Input data inversion function (capable of controlling by each input port) (POL21, POL22)
Apply for heavy load, light load
Semi slim-chip shaped
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
COF (COF package)
碌
PD160061N-xxx
碌
PD160061NL-xxx
Remark
The TCP鈥檚 external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15843EJ2V0DS00 (2nd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The mark
鈽?/div>
shows major revised points.
2003
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