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UPA1742TP Datasheet

  • UPA1742TP

  • SWITCHING N-CHANNEL POWER MOSFET

  • 7頁

  • NEC   NEC

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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
碌
PA1742TP
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8, 9 ; Drain
The
碌
PA1742TP is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for high voltage applications
such as DC/DC converter.
1.49 鹵0.21
2.0 鹵0.2
2.9 MAX.
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power HSOP8
8
9
4.1 MAX.
碌
PA1742TP
5
ABSOLUTE MAXIMUM RATINGS (T
A
= 25擄C, unless otherwise noted. All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25擄C)
Drain Current (pulse)
Note1
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
Note2
250
鹵30
鹵7.0
鹵21
24
1.0
150
鈭?5
to +150
7.0
4.9
7.0
V
V
A
A
W
W
擄C
擄C
A
mJ
A
1.1 鹵0.2
鈥?/div>
High voltage: V
DSS
= 250 V
鈥?/div>
Gate voltage rating: 鹵30 V
鈥?/div>
Low on-state resistance
R
DS(on)
= 0.55
鈩?/div>
MAX. (V
GS
= 10 V, I
D
= 3.5 A)
鈥?/div>
Low input capacitance
C
iss
= 460 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
鈥?/div>
Built-in gate protection diode
鈥?/div>
Small and surface mount package (Power HSOP8)
1.44 TYP.
FEATURES
1
5.2
+0.17
鈥?.2
4
0.8 鹵0.2
S
+0.10
鈥?.05
6.0 鹵0.3
4.4 鹵0.15
0.05 鹵0.05
0.15
1.27 TYP.
0.40
1
+0.10
鈥?.05
0.10 S
0.12 M
4
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation (T
C
= 25擄C)
Total Power Dissipation (T
A
= 25擄C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
Note4
Note4
P
T2
T
ch
T
stg
I
AS
E
AS
I
AR
Gate
Body
Diode
Gate
Protection
Diode
Source
Repetitive Avalanche Current
Repetitive Pulse Avalanche Energy
E
AR
4.9
mJ
Notes 1.
PW
鈮?/div>
10
碌
s, Duty Cycle
鈮?/div>
1%
2.
Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm
3.
Starting T
ch
= 25擄C, V
DD
= 125 V, R
G
= 25
鈩?
L = 100
碌
H, V
GS
= 20
鈫?/div>
0 V
4.
T
ch(peak)
鈮?/div>
150擄C, L = 100
碌
H
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16325EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2002

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