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UPA1740TP Datasheet

  • UPA1740TP

  • SWITCHING N-CHANNEL POWER MOSFET

  • 8頁

  • NEC   NEC

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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
碌
PA1740TP
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
: Source
4
: Gate
5, 6, 7, 8, 9 : Drain
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The
碌
PA1740TP is N-channel MOS FET device that features a
low on-state resistance and excellent swiching characteristics, and
designed for high voltage applications such as DC/DC converter.
FEATURES
鈥?/div>
High voltage: V
DSS
= 200 V
鈥?/div>
Gate voltage rating:
鹵30
V
鈥?/div>
Low on-state resistance
R
DS(on)
= 0.44
鈩?/div>
MAX. (V
GS
= 10 V, I
D
= 3.5 A)
鈥?/div>
Low input capacitance
C
iss
= 420 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
鈥?/div>
Built-in gate protection diode
鈥?/div>
Small and surface mount package (Power HSOP8)
鈥?/div>
Avalanche capability rated
1.49 鹵0.21
1.44 TYP.
1
5.2
+0.17
鈥?.2
4
0.8 鹵0.2
S
+0.10
鈥?.05
6.0 鹵0.3
4.4 鹵0.15
0.05 鹵0.05
0.15
1.27 TYP.
0.40
1
+0.10
鈥?.05
0.10 S
0.12 M
2.0 鹵0.2
2.9 MAX.
ORDERING INFORMATION
PART NUMBER
碌
PA1740TP
PACKAGE
Power HSOP8
8
9
4.1 MAX.
5
ABSOLUTE MAXIMUM RATINGS (T
A
= 25擄C, Unless otherwise noted, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25擄C)
Drain Current (pulse)
Note1
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
Note2
200
鹵30
鹵7.0
鹵21
22
1.0
150
鈥?5 to + 150
7.0
4.9
7.0
2.2
V
V
A
A
W
W
擄C
擄C
A
mJ
A
mJ
Gate
Protection
Diode
Source
Gate
Body
Diode
Total Power Dissipation (T
C
= 25擄C)
Total Power Dissipation (T
A
= 25擄C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
Note4
Note4
EQUIVALENT CIRCUIT
Drain
I
AS
E
AS
I
AR
E
AR
Repetitive Avalanche Current
Repetitive Avalanche Energy
Notes 1.
2.
3.
4.
PW
鈮?/div>
10
碌
s, Duty Cycle
鈮?/div>
1%
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
Starting T
ch
= 25擄C, V
DD
= 100 V, R
G
= 25
鈩?
L = 100
碌
H, V
GS
= 20
鈫?/div>
0 V
T
ch
鈮?/div>
125擄C, V
DD
= 100 V, R
G
= 25
鈩?/div>
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15937EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP(K)
Printed in Japan
1.1 鹵0.2
4
漏
2001

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