鈥?/div>
Small and surface mount package (Power SOP8)
PACKAGE DRAWING (Unit : mm)
8
5
1,2,3 ; Source
; Gate
4
5,6,7,8 ; Drain
1
4
5.37 Max.
+0.10
鈥?.05
6.0 鹵0.3
4.4
0.8
0.15
PART NUMBER
PACKAGE
Power SOP8
1.8 Max.
ORDERING INFORMATION
1.44
0.05 Min.
碌
PA1710AG
0.5 鹵0.2
0.10
1.27 0.78 Max.
0.40
+0.10
鈥?.05
0.12 M
ABSOLUTE MAXIMUM RATINGS (T
A
= 25擄C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
EQUIVARENT CIRCUIT
Drain
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
鈥?0
鹵20
鹵5.0
鹵20
2.0
150
鈥?5 to + 150
V
V
A
A
W
擄C
擄C
Gate
Protection
Diode
Gate
Body
Diode
Total Power Dissipation (T
A
= 25擄C)
Channel Temperature
Storage Temperature
Source
Notes 1.
PW
鈮?/div>
10
碌
s, Duty Cycle
鈮?/div>
1 %
2.
Mounted on ceramic substrate of 1200 mm x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
2
Document No.
G11497EJ1V1DS00 (1st edition)
Date Published November 1998 NS CP(K)
Printed in Japan
漏
1995
next