UG2 Series
0.5碌m ULC Series
Description
The UG2 series of ULCs is well suited for conversion of
medium- to-large sized CPLDs and FPGAs. Devices are
implemented in high-performance CMOS technology
with 0.5-碌m (drawn) channel lengths, and are capable of
supporting flip-flop toggle rates of 625 MHz at 5V and
360 MHz at 3.3V, operating clock frequencies up to 150
MHz and input to output delays as fast as 5 ns, 200 ps at
5V.
The architecture of the UG2 series allows for efficient
conversion of many PLD architecture and FPGA device
types with higher IO count. A compact RAM cell, along
with the large number of available gates allows the
implementation of RAM in FPGA architectures that
support this feature, as well as JTAG boundary-scan and
scan-path testing.
Conversion to the UG2 series of ULC can provide a
significant reduction in operating power when
compared to the original PLD or FPGA. This is
especially true when compared to many PLD and CPLD
architecture devices, which typically consume 100 mA
or more even when not being clocked. The UG2 series
has a very low standby consumption of 0.4 nA/gate
typically commercial temp, which would yield a
standby current of 0.4 nA/gate, 4 mA on a 10,000 gate
design. Operating consumption is a strict function of
clock frequency, which typically results in a power
reduction of 50% to 90% depending on the device being
compared.
The UG2 series provides several options for output
buffers, including a variety of drive levels up to 24 mA.
Schmitt trigger inputs are also an option. A number of
techniques are used for improved noise immunity and
reduced EMC emissions, including: several
independent power supply busses and internal
decoupling for isolation; slew rate limited outputs are
also available as required.
The UG2 series is designed to allow conversions of high
performance 3-V devices as well as 5-V devices.
Support of mixed supply conversions is also possible,
allowing optimal trade-offs between speed and power
consumption.
Features
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High performance ULC family suitable for
medium- to large-sized CPLDs and FPGAs
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Conversions to over 700,000 FPGA gates
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Pin counts to over 582 pins
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Any pin-out matched due to limited number of
dedicated pads
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Full range of packages: DIP, SOIC, LCC/PLCC,
PQFP/TQFP, PGA/PPGA, PBGA/CABGA
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3.3V and/or 5.0V operation.
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Low quiescent current: 0.04 nA/gate
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Available in commercial, industrial, automotive,
military and space grades.
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0.5
碌m
Drawn CMOS, 3 Metal Layers
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Library Optimised for Synthesis, Floor Plan &
Automatic Test Generation (ATG)
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High Speed Performances:
鈥?200 ps Typical Gate Delay @5 V
鈥?Typical 625 MHz Toggle Frequency @5V
and 360 MHz @3.3 V
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High System Frequency Skew Control:
鈥?Clock Tree Synthesis Software
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3 & 5 Volts Operation; Single or Dual Supply
Modes
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Low Power Consumption:
鈥?0.6
碌W/Gate/MHz
@3 V
鈥?2.2
碌W/Gate/MHz
@5 V
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Power on Reset
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Standard 3, 6, 12 and 24mA I/Os
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CMOS/TTL/PCI Interface
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ESD (2 kV) and Latch鈥搖p Protected I/O
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High Noise & EMC Immunity:
鈥?I/O with Slew Rate Control
鈥?Internal Decoupling
鈥?Signal Filtering between Periphery & Core
鈥?Application Dependent Supply Routing &
Several
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Rev.L
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