鈥?/div>
Differential Failsafe Bias
DESCRIPTION
The UCC561 LVD Regulator set is designed to provide the correct refer-
ences voltages and bias currents for LVD termination resistor networks
(475 , 121 and 475 ). The device also provides a 1.3V output for Diff
Sense signaling. With the proper resistor network, the UCC561 solution will
meet the common mode bias impedance, differential bias, and termination
impedance requirements of SPI-2 (Ultra2) and SPI-3 (Ultra3).
This device incorporates into a single monolith, two sink/source reference
voltage regulators, a 1.3V buffered output and protection features. The pro-
tection features include thermal shut down and active current limiting cir-
cuitry. The UCC561 is offered in 16-pin SOIC(DP) package.
BLOCK DIAGRAM
REF 1.3V
TRMPWR
2.7V < 5.25V
2
REF 1.75V
1.75V +/鈥?0mV
200mA SOURCE/SINK
1.3V +/鈥?0.1V
7
DIFSENS
6
REG1
SOURCE/SINK REGULATOR
REF 0.75V
0.75V +/鈥?0mV
200mA SOURCE/SINK
3
REG2
4
PGND
UDG-98093
SLUS413 - MAY 1999